Conventionally, a multiphase clock is used to extract data signal in PLL (phase-locked loop). As PLL has an important place in the field of information communications, various types of multiphase clock generating circuits, which are used mainly to extract data, have been developed.
Examples of conventional multiphase clock generating circuit are explained in reference to FIGS. 1 and 2.
FIG. 1 is a block diagram showing the composition of a conventional multiphase clock generating circuit. As shown in FIG. 1, the conventional multiphase clock generating circuit is composed of a clock generating section 1000 that is fed with input clock signal and then outputs N output clock signals .phi.100 to .phi.N00 which have a frequency nearly equal to that of input clock signal and whose phases are shifted sequentially by 360/N, where N is an arbitrary positive integer of 2 or more, an input side M-dividing circuit 2000 that divides this input clock signal into M frequencies to output an input side M-divided signal 7000, where M is a positive integer, an output side M-dividing circuit 3000 that is fed with output clock signal 8000 output from the clock generating section 1000 and then divides the frequency of output clock signal 8000 by M to output an output side M-divided signal 10000, a phase comparison circuit 4000 that compares the phases of input side M-divided clock signal 7000 and output side M-divided clock signal 10000 and then outputs a phase comparison information 11000, and a control circuit 5000 that outputs N control signals 1200-1 to 1200-N based on the phase comparison information 11000 output from the phase comparison circuit 4000.
Next, the operations of respective components of the conventional multiphase clock generating circuit in FIG. 1 are explained in detail.
First, the input side M-dividing circuit 2000 divides the frequency of input clock signal by M to make the input side M-divided clock signal 7000, then outputting it to the phase comparison circuit 4000. Also, the input side M-dividing circuit 2000 outputs a control clock signal 13000 to the control circuit 5000.
Then, the output side M-dividing circuit 3000 divides the frequency of output clock signal 8000 by N to make the output side M-divided clock signal 10000, then outputting it to the phase comparison circuit 4000.
Then, the phase comparison circuit 4000 compares the phase difference between the input side M-divided clock signal 7000 and the output side M-divided clock signal 10000, then outputting the phase comparison information 11000 to indicate the phase difference to the control circuit 5000.
The control circuit 5000 outputs the control signals 1200-1 to 1200-N to the clock generating section 1000, based on the phase comparison information 11000. The clock generating section 1000 outputs generating N output clock signals .phi.100, . . . , .phi.N00, which have a frequency nearly equal to that of input clock signal and whose phases are shifted sequentially by 360/N degree, from input clock signal based on the control signals 1200-1 to 1200-N.
The operation of the clock generating section 1000 in FIG. 1 is further explained in detail, referring to FIG. 2. FIG. 2 is a block diagram showing a composition of the clock generating section 1000 in FIG. 1.
As shown in FIG. 2, the clock generating section 1000 in FIG. 1 is composed of N adjustable delay circuits 20100-1, 20100-2, 20100-3, . . . , 20100-N, where N is an arbitrary integer of 1 or more, that are fed with input clock signal like a pipeline and then output delaying the input clock signal by the control of N control signals 1200-1 to 1200-N.
First, as shown in FIG. 2, the clock generating section 1000 provided for the conventional multiphase clock generating circuit outputs the unaltered input clock signal as output clock signal .phi.100.
Then, delaying the input clock signal by the adjustable delay circuit 20100-1 based on the control signal 1200-1 supplied, output clock signal .phi.200 is output from the adjustable delay circuit 20100-1.
Then, delaying the output clock signal .phi.200 output from the adjustable delay circuit 20100-1 by the adjustable delay circuit 20100-2 based on the control signal 1200-2 supplied, output clock signal .phi.300 is output from the adjustable delay circuit 20100-2.
Below, in like manner, output clock signals .phi.400, . . . , .phi.N00 are output in sequence. Thus, from the conventional multiphase clock generating circuit, N output clock signals which have a frequency nearly equal to that of input clock signal and whose phases are shifted sequentially by 360/N can be output.
In recent years, PLLs, which extract data signal, using multiphase clock have been researched a great deal. Many of these PLLs use an analogue circuit, such as VCO, when generating multiphase clock. Therefore, in such a case that the multiphase clock generating circuit is integrated in a digital logic LSI, the affect to the analogue circuit, such as a noise occurred in digital logic and a noise from power supply, is necessary to solve. However, it is very difficult to solve it.
For example, when the affect to the analogue circuit, such as a noise occurred in digital logic and a noise from power supply, is not solved sufficiently, in FIG. 1, the amount T of delay in the clock generating section 1000 may be not equal to one-cycle delay amount T but equal to two-cycle or three-cycle delay amount 2T or 3T. Therefore, there occurs a problem that the multiphase clock signal output does not correspond to the N-phase clock signal.
Further, in the conventional multiphase clock generating circuit, when the input clock signal whose one cycle is to be equally divided is a high-speed input clock signal (with a high frequency), the minimum value of delay amount of the clock generating section 1000 may exceed a cycle T. Therefore, it causes a failure in making multiphase clock.